View AK5730_7817366.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

[AK5730] rev 0.8 2013/06 - 1 - general description the AK5730 features a 4-channel diffe rential adc with sar adc for dc measurement. differential adc supports line and microphone-input, making it ideal fo r microphone array applications. tdm audio format makes it easy to connect with dsp. features 1. audio adc - 4-channel audio adc - full-differential input - input voltage: mic: 1.65vrms, line and phone: 3vrms(with external resistors) programmable boost input: 11.7vrms(with external resistors) programmable - adc performance: s/(n+d): typ 92db dr, s/n: typ 100db - digital hpf for dc-offset cancellati on: fc=1hz with individual on/off 2. sar adc - 1ch sar adc with 9:1 mux - reference voltage: ground 3. sampling rate: 8khz ~ 48khz 4. master clock: 256fs, 384fs, 512fs or internal pll 5. master/slave mode 6. audio interface format: msb first, 2?s complement - 24bit i 2 s - 24bit tdm interface up to 4 ics cascade 7. channel independent microphone diagnostics - open microphone - shorts to battery - shorts to ground - shorts across inputs - microphone bias over current - over temperature 8. programmable microphone bias: 5v to 9v with 0.5v step 9. p i/f: i2c bus (ver 1.0, 400khz mode) or spi 10. power supply: vdd: 3.0 3.6v 11. ta = ? 40 105 c 12. package: 48pin lqfp AK5730 4-channel differential audio adc for line & mic inputs
[AK5730] rev 0.8 2013/06 - 2 - block diagram vss1 sdto1 lrlk bick(64-512fs) iis/tdm out iic or spi i/f sda/cdti scl/cclk hpf, lpf, gain in1p in1n mic bias, cp adc4 sar adc in4p in4n mic. diags cad0/csn +5.0~9.0v mux 1 2 7 8 max: 10ma x 4mic mic line tdmi pll int cad1/cdto vbatm 9 battery sdto2 avdd vss2 dvdd vref pdn adc1 mclki mux mclk cp2 cn2 cvp1 msn cp1 cn1 cvp2 inm1p inm1n inm4p inm4n + - + - spi amp. amp. figure 1. block diagram
[AK5730] rev 0.8 2013/06 - 3 - pin layout mpwr 37 vref 36 38 cvp2 39 nc 40 inm1p 41 in1p 42 43 in1n 44 inm1n 45 inm2p 46 in2p 47 nc 35 34 33 32 31 30 29 28 27 26 vrefl 1 inm3p 2 in3p 3 msn 4 inm4p 5 vss1 6 inm4n 7 vbatm 8 in4n 9 in4p 10 inm3n 11 23 22 21 20 19 18 17 16 15 14 13 cad1/cdto pdn cad0/csn top view in2n 48 in3n 12 24 25 inm2n cp2 a k5730vq tdmi int bick mclk sdto1 lrck sdto2 a vdd spi dvdd vss2 nc cn2 scl/cclk sda/cdti nc cvp1 cp1 cn1
[AK5730] rev 0.8 2013/06 - 4 - no. pin name i/o function 1 vrefl i adc reference pin. 0v 2 inm3p i ch3 positive input monitor pin 3 in3p i ch3 positive input pin (with dc cut capacitor) 4 in3n i ch3 negative input pin (with dc cut capacitor) 5 inm3n i ch3 negative input monitor pin 6 msn i master/slave control pin 7 inm4p i ch4 positive input monitor pin 8 in4p i ch4 positive input pin (with dc cut capacitor) 9 in4n i ch4 negative input pin (with dc cut capacitor) 10 inm4n i ch4 negative input monitor pin 11 vss1 - ground pin 1. 0v 12 vbatm i b attery power monitor pin 13 avdd - analog power supply pin, 3.0 3.6v normally connected to vss1 with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 14 spi i control mode select pin ?l?: i 2 c bus or parallel control mode, ?h?: 4-wire serial control mode 15 pdn i power-down mode pin when at ?l?, the AK5730 is in the power-down mode and is held in reset. the AK5730 should always be reset upon power-up. cad0 i (spi pin = ?l?) chip address 0 pin 16 csn i (spi pin = ?h?) chip select pin in serial control mode cad1 i (spi pin = ?l?) chip address 1 pin 17 cdto o (spi pin = ?h?) control data output pin 18 tdmi i tdm data input pin 19 mclk i master clock input pin 20 bick i/o audio serial data clock pin 21 lrck i/o channel clock pin adc audio serial data output1 pin 22 sdto1 o test mode digital output pin adc audio serial data output2 pin 23 sdto2 o test mode digital output pin 24 int o interrupt signal output pin normally connected to dvdd(3.3v) through 10k resistor externally. sda i/o (spi pin = ?l?) control data input/output pin 25 cdti i (spi pin = ?h?) control data input pin scl i (spi pin = ?l?) control data clock pin 26 cclk i (spi pin = ?h?) control data clock pin 27 nc - this pin should be connected to vss1. pin/function
[AK5730] rev 0.8 2013/06 - 5 - no. pin name i/o function 28 cn2 i negative charge pump capacitor terminal pin 2 connect to cp2 with a 2.2 f capacitor that should have the low esr (equivalent series resistance) over all temperature range. when this capacitor has the polarity, the positive polarity pin should be connected to the cp2 pin. non polarity capacitors can also be used. * the maximum bias voltage of this pin is 7.2v. the capacitance variation of an external capacitor should be in the range of 2.2 f +20% and -40% including the difference by a tolerance, a rate of tem perature change and a bias voltage. 29 nc - this pin should be connected to vss1. 30 vss2 - digital ground pin and charge pump ground pin , 0v 31 dvdd - digital power supply pin and charge pump circuit positive power supply pin 3.0v 3.6v normally connected to vss2 with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 32 cn1 i positive charge pump capacitor terminal pin 1 connect to cn1 with a 2.2 f capacitor that should have the low esr (equivalent series resistance) over all temperature range. when this capacitor has the polarity, the positive polarity pin should be connected to the cn1 pin. non polarity capacitors can also be used. * the maximum bias voltage of this pin is 3.6v. the capacitance variation of an external capacitor should be in the range of 2.2 f +20% and -40% including the difference by a tolerance, a rate of temperature change and a bias voltage. 33 cp1 i negative charge pump capacitor terminal pin 1 connect to cp1 with a 2.2 f capacitor that should have the low esr (equivalent series resistance) over all temperature range. when this capacitor has the polarity, the positive polarity pin should be connected to the cp1 pin. non polarity capacitors can also be used. * the maximum bias voltage of this pin is 3.6v. the capacitance variation of an external capacitor should be in the range of 2.2 f +20% and -40% including the difference by a tolerance, a rate of temperature change and a bias voltage. 34 cvp1 o charge pump circuit positive voltage output pin 1 connect to vss2 with a 2.2 f capacitor that should have the low esr (equivalent series resistance) over all temperature range. when this capacitor has the polarity, the positive polarity pin should be connected to the vss2 pin. non polarity capacitors can also be used. * the maximum bias voltage of this pin is 7.2v. the capacitance variation of an external capacitor should be in the range of 2.2 f +20% and -40% including the difference by a tolerance, a rate of temperature change and a bias voltage. 35 nc - this pin should be connected to vss1. 36 mpwr o mic power supply pin normally connected to vss1 with a 1 f ceramic capacitor. * the maximum bias voltage of this pin is 10v. the capacitance variation of an external capacitor should be in the range of 1 f +20% and -40% including the difference by a tolerance, a rate of temperature change and a bias voltage.
[AK5730] rev 0.8 2013/06 - 6 - no. pin name i/o function 37 cp2 i positive charge pump capacitor terminal pin 2 connect to cn2 with a 2.2 f capacitor that should have the low esr (equivalent series resistance) over all temperature range . when this capacitor has the polarity, the positive polarity pin should be connected to the cn2 pin. non polarity capacitors can also be used. * the maximum bias voltage of this pin is 7.2v. the capacitance variation of an external capacitor should be in the range of 2.2 f +20% and -40% including the difference by a tolerance, a rate of temperature change and a bias voltage. 38 cvp2 o charge pump circuit positive voltage output pin 2 connect to vss2 with a 2.2 f capacitor that should have the low esr (equivalent series resistance) over all temperature range . when this capacitor has the polarity, the positive polarity pin should be connected to th e vss2 pin. non polarity capacitors can also be used. * the maximum bias voltage of this pin is 7.2v. the capacitance variation of an external capacitor should be in the range of 2.2 f +20% and -40% including the difference by a tolerance, a rate of temperature change and a bias voltage. 39 nc - this pin should be connected to vss1. 40 inm1p i ch1 positive input monitor pin 41 in1p i ch1 positive input pin (with dc cut capacitor) 42 in1n i ch1 negative input pin (with dc cut capacitor) 43 inm1n i ch1 negative input monitor pin 44 vref o voltage reference pin for mpwr. normally connected to vss1 with a 1.0 f ceramic capacitor. 45 inm2p i ch2 positive input monitor pin 46 in2p i ch2 positive input pin (with dc cut capacitor) 47 in2n i ch2 negative input pin (with dc cut capacitor) 48 inm2n i ch2 negative input monitor pin note 1. all digital input pins should not be left floating. nc pin (no internal bonding).
[AK5730] rev 0.8 2013/06 - 7 - absolute maximum ratings (vss1=vss2=0v; note 2 ) parameter symbol min max unit power supplies: analog avdd ? 0.3 4.6 v digital charge pump dvdd cvdd ? 0.3 -0.3 4.6 4.6 v v input current, any pin except supplies iin - 10 ma analog input voltage ( note 3 ) vina ? 0.3 cvp1+0.3 v digital input voltage vind ? 0.3 dvdd+0.3 v ambient temperature (powered applied) ta ? 40 105 c storage temperature tstg ? 65 150 c note 2. all voltages with respect to ground. vss1 and vss2 must be connected to the same analog ground plane. note 3. cvp1: cvp1 pin voltage. the internal positive power supply generating ci rcuit provides positive power supply (cvp1). mode cvp1 pin voltage power-down (pdn pin and rstn bit control) avdd normal operation 1.67 x avdd cvp1 pin voltage warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommended operating conditions (vss1=vss2 =0v; note 2 ) parameter symbol min typ max unit power supplies analog avdd 3.0 3.3 3.6 v ( note 4 ) digital, charge pump dvdd 3.0 3.3 3.6 v note 2. all voltages with respect to ground. vss1 and vss2 must be connected to the same analog ground plane. note 4. the avdd, dvdd must be the same voltage. warning: akm assumes no responsibility for the us age beyond the conditions in this datasheet.
[AK5730] rev 0.8 2013/06 - 8 - analog characteristics (ta=25 c; avdd=dvdd =3.3v; vss1=vss2=vss3=0v; mcki=512fs, fs=48khz, bclk=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz; unless otherwise specified; gain bit = ?0?) parameter min typ max unit adc analog characteristics (ac): resolution - - 24 bits differential, note 5 1.55 1.65 1.75 vrms input voltage single-ended, note 6 0.77 0.82 0.87 vrms gain mode, note 7 0.51 0.55 0.59 vrms input impedance 1.0 1.4 m ? 0.5dbfs differential 86 92 - db s/(n+d) ? 0.5dbfs single-ended 86 92 - db ? 0.5dbfs gain mode 86 92 ? 60dbfs, a-weighted differential 93 100 - db dynamic range ? 60dbfs, a-weighted single-ended 92 99 - db ? 60dbfs, a-weighted gain mode 92 98 a-weighted differential 93 100 - db s/n a-weighted single-ended 92 99 - db 10mvrms input, a-weighted gain mode 57 63 - db interchannel isolation 90 100 - db interchannel gain mismatch 0 0.3 db 1khz, differential. note 8 70 85 db 20khz, differential. note 8 70 85 db 1khz, single-ended, note 8 65 80 db cmrr 20khz, single-ended, note 8 55 65 db 1khz, gain mode, note 9 65 80 db 20khz, gain mode, note 9 65 80 db psrr (1khz, note 10 ) 50 db mic power supply: mbs3-0 bits= ?0000? 4.90 5 5.10 v mbs3-0 bits= ?0001? 5.39 5.5 5.61 v mbs3-0 bits= ?0010? 5.88 6 6.12 v mbs3-0 bits= ?0011? 6.37 6.5 6.63 v mbs3-0 bits= ?0100? 6.86 7 7.14 v mbs3-0 bits= ?0101? 7.35 7.5 7.65 v mbs3-0 bits= ?0110? 7.84 8 8.16 v mbs3-0 bits= ?0111? 8.33 8.5 8.67 v output dc voltage ( note 11 ) mbs3-0 bits= ?1000? 8.78 9 9.22 v microphone current (for 4 channels) 0.1 40 ma output noise level (a-weighted) -100 -94 dbv sar adc characteristics (dc): resolution - - 12 bits input voltage ( note 12 ) 3.2 3.3 3.4 v integral nonlinearity (inl) error -4 +5 lsb differential nonlinearity (dnl) error -2 +2 lsb note 5. the voltage difference between in*p and in*n pins. input voltage should be adjusted with external resistors. input voltage is proportional to avdd voltage. vin = 0.5 avdd vrms (typ). full scale: -0.034db note 6. single-ended in*p pin, in*n pin must be connected to signal common. input voltage should be adjusted with external resistors. when std* bit = ?1?, input voltage is proportional to avdd voltage. vin = 0.25 avdd vrms (typ). full scale: -0.034db note 7. the voltage difference between in*p and in*n pins. i nput voltage should be adjusted with external resistors. when gain* bit = ?1?, input voltage = 0.55vrms = 0.167 avdd vrms (typ). full scale: -0.034db note 8. the 1khz, 1.0vpp signal is applied to in*n and in*p with same phase. the cmrr is measured as the attenuation level from 0db = -7.5dbfs(since the normal 1vpp= -7.5dbfs). note 9. the 1khz, 0.5vpp signal is applied to in+. in- pin must be connected to be signal common. the cmrr is measured as the attenuation level from 0db = -4dbfs(since the normal 1vpp=-4dbfs).
[AK5730] rev 0.8 2013/06 - 9 - note 10. the psrr is applied to avdd and dvdd with 1khz, 100mvpp. note 11. when mbs3-0 bits = ?0000? / ?0001? / ?0010? / ?0011? / ?0100? / ?0101? / ?0110? / ?0111?/ ?1000?, output dc voltage(typ) is 1.52 / 1.67 / 1.82 / 1.97 / 2.12 / 2.27 / 2.42 / 2.58/ 2.73 avdd(v). when mbs3-0 bits = ?0000? / ?0001? / ?0010? / ?0011? / ?0100? / ?0101? / ?0110? / ?0111?, output dc voltage(min, max) is 2.0% of output dc voltage(typ). when mbs3-0 bits = ?1000?, output dc voltage(min, max) is 2.5% of output dc voltage (typ). note 12. input voltage should be adjusted with external resistors. the input voltage range is 0 to avdd. vin = 1.00 avdd (vpp). the sar adc operates at not less than 100 mv.
[AK5730] rev 0.8 2013/06 - 10 - filter characteristics (ta=25 c ; avdd=dvdd=3.0 3.6v; fs=48khz) parameter symbol min typ max unit adc digital filter (decimation lpf): passband ( 1 note 13 ) 0.13db -0.2db -3.0db pb 0 - - 20.0 23.0 18.0 - - khz khz khz stopband sb 28 khz passband ripple pr 0.04 db stopband attenuation sa 68 db group delay ( 1 note 14 ) gd 16.4 1/fs group delay distortion gd 0 s adc digital filter (hpf): frequency response ( 1 note 13 ) -3db -0.1db fr 1.0 7.1 hz hz note 13. the passband and stopband frequencies scale with fs. for example, 21.8khz at ?0.1db is 0.454 x fs. note 14. the calculating delay time which occurred by digital filtering. this time is from setting the input of analog signal to setting the 24bit data of both channels to the output register. dc characteristics (ta=-40 c ~+105 c; avdd=dvdd=3.0 3.6v) parameter symbol min typ max unit high-level input voltage low-level input voltage vih vil 70%dvdd - - - - 30%dvdd v v high-level output voltage ( iout=-400 a) low-level output voltage (iout= -400 a(except sda, int pin), 3ma(sda, int pin)) voh vol dvdd-0.4 - - - 0.4 v v input leakage current iin - - 10 a (ta=25 c; avdd=dvdd=3.3v ) power supplies parameter min typ max unit power supply current normal operation (pdn pin = ?h?) dvdd (microphone current=40ma) dvdd (microphone current=100ua) avdd power-down mode (pdn pin = ?l?; note 15 ) dvdd+avdd dvdd avdd 180 18 9 3 0 220 27 13.5 100 ma ma ma a a a note 15. all digital inputs including clock pins (mclk, bick, lrck and tdmi) are held at dvdd or vss2.
[AK5730] rev 0.8 2013/06 - 11 - switching characteristics (ta=-40 +105 c; avdd=dvdd=3.0 3.6v; c l =20pf; unless otherwise specified) parameter symbol min typ max unit master clock timing external clock 256fs: pulse width low pulse width high 384fs: pulse width low pulse width high 512fs: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 2.048 32 32 3.072 22 22 4.096 16 16 12.288 18.432 24.576 mhz ns ns mhz ns ns mhz ns ns lrck timing (slave mode) stereo mode (tdm1/0 bit = ?00?) frequency duty cycle fs duty 8 45 48 55 khz % tdm256 mode ( note 16 ) (tdm1/0 bit = ?01?) lrck frequency ?h? time ?l? time fsn tlrh tlrl 8 1/256fs 1/256fs 48 khz ns ns tdm512 mode ( note 16 ) (tdm1/0 bit = ?10?) lrck frequency ?h? time ?l? time fsn tlrh tlrl 8 1/512fs 1/512fs 48 khz ns ns lrck timing (master mode) stereo mode (tdm1/0 bit = ?00?) normal speed mode duty cycle fsn duty 8 - 50 48 - khz % tdm256 mode ( note 16 ) (tdm1/0 bit = ?01?) lrck frequency ?h? time ( note 17 ) fsn tlrh 8 1/8fs 48 khz ns tdm512 mode ( note 16 ) (tdm1/0 bit = ?10?) lrck frequency ?h? time ( note 17 ) fsn tlrh 8 1/16fs 48 khz ns note 16. master clock should be input the 256fs/512fs in master mode. note 17. if the format is i 2 s, it is ?l? time.
[AK5730] rev 0.8 2013/06 - 12 - parameter symbol min typ max unit audio interface timing (slave mode) stereo mode (tdm1/0 bit = ?00?) bick period bick pulse width low pulse width high lrck edge to bick ? ? ( note 18 ) bick ? ? to lrck edge ( note 18 ) lrck edge to sdto(msb)(except i 2 s mode) bick ? ? to sdto tbck tbckl tbckh tlrb tblr tlrs tbsd 320 128 128 20 20 20 20 ns ns ns ns ns ns ns tdm256 mode (tdm1/0 bit = ?01?) bick period bick pulse width low pulse width high lrck edge to bick ? ? ( note 18 ) bick ? ? to lrck edge ( note 18 ) sdto setup time bick ? ? sdto hold time bick ? ? tdmi hold time tdmi setup time tbck tbckl tbckh tlrb tblr tbss tbsh tsdh tsds 80 32 32 20 20 12 10 20 20 ns ns ns ns ns ns ns ns ns tdm512 mode (tdm1/0 bit = ?10?) bick period bick pulse width low pulse width high lrck edge to bick ? ? ( note 18 ) bick ? ? to lrck edge ( note 18 ) sdto setup time bick ? ? sdto hold time bick ? ? tdmi hold time tdmi setup time tbck tbckl tbckh tlrb tblr tbss tbsh tsdh tsds 40 16 16 10 10 6 5 10 10 ns ns ns ns ns ns ns ns ns audio interface timing (master mode) stereo mode (tdm1/0 bit = ?00?) bick frequency bick duty bick ? ? to lrck bick ? ? to sdto fbck dbck tmblr tbsd - - ? 20 ? 20 64fs 50 - - - - 20 20 hz % ns ns tdm256 mode (tdm1/0 bit = ?01?) bick frequency bick duty bick ? ? to lrck sdto setup time bick ? ? sdto hold time bick ? ? tdmi hold time tdmi setup time fbck dbck tmblr tbss tbsh tsdh tsds - - -20 12 10 20 20 256fs 50 - - - - - - 20 20 - - - hz % ns ns ns ns ns tdm512 mode (tdm1/0 bit = ?10?) bick frequency bick duty bick ? ? to lrck sdto setup time bick ? ? sdto hold time bick ? ? tdmi hold time tdmi setup time fbck dbck tmblr tbss tbsh tsdh tsds - - -10 6 5 10 10 512fs 50 - - - - - 10 - - - - hz % ns ns ns ns note 18. bick rising edge must not occur at the same time as lrck edge.
[AK5730] rev 0.8 2013/06 - 13 - parameter symbol min typ max unit control interface timing (4-wire serial mode) cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? cdto delay csn ? ? to cdto hi-z tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 50 50 150 50 50 45 70 ns ns ns ns ns ns ns ns ns ns control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 19 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu :sta thd :dat tsu :dat tr tf tsu:sto tsp :i 2 c cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 - 400 - - - - - - - 1.0 0.3 - 50 400 khz s s s s s s s s s s ns pf power-down & reset timing pdn pulse width ( note 20 ) pdn ? ? to sdto valid (fs1/0bit=?00?) ( note 21 ) pdn ? ? to sdto valid (fs1/0bit=?01?) ( note 21 ) pdn ? ? to sdto valid (fs1/0bit=?10?) ( note 21 ) pulse width of spike noise suppressed by input filter tpd tpdv tsp :pd 150 0 3153 2098 1729 20 ns 1/fs 1/fs 1/fs ns note 19. data must be held for sufficient tim e to bridge the 300 ns transition time of scl. note 20. the AK5730 can be reset by se tting the pdn pin to ?l? upon power-up. note 21. these cycles are the numbers of lrck rising from the pdn pin rising. note 22. i 2 c-bus is a trademark of nxp b.v.
[AK5730] rev 0.8 2013/06 - 14 - timing diagram 1/fclk tclkl vih tclkh mcki vil 1/fs lr ck vih vil tbck tbc kl vih tbckh bic k vil tdlrkl tdlrkh duty = tdlrkh (or tdlrkl) x fs x 100 figure 2. clock timing (tdm1/0 bits = ?00? & slave mode) 1/fclk tc lkl vih tclkh mcki vil 1/fs lrc k vih vil tlr l tlrh tbck tbc kl vih tbckh bi ck vil figure 3. clock timing (except tdm1/0 bits = ?00? & slave mode)
[AK5730] rev 0.8 2013/06 - 15 - 1/fclk tclkl vih tclkh mcki vil 1/fbck tdbckl tdbckh bick 50%dvdd 1/fs lrck 50%dvdd tdlrkl tdlrkh dlrk = tdlrkh (or tdlrkl) x fs x 100 dbck = tdbckh (or tdbckl) x fs x 100 figure 4. clock timing (tdm1/0 bits = ?00? & master mode) 1/fclk tclkl vih tclkh mcki vil 1/fs lrck 50%dvdd tlrh 1/fbck tdbckl tdbckh bick 50%dvdd dbck = tdbckh (or tdbckl) x fs x 100 figure 5. clock timing (except tdm1/0 bits = ?00? & master mode)
[AK5730] rev 0.8 2013/06 - 16 - tlrb lrck vih bick vil tlrs sdto 50%d vdd tbsd vih vil tblr figure 6. audio interface timing (tdm 1/0 bits = ?00? & slave mode) tlrb lrck vih bick vil sdto 50%dvdd tbss vih vil tblr tsds tdmi vih vil tsdh tbsh figure 7. audio interface timing (except tdm1/0 bits = ?00? & slave mode)
[AK5730] rev 0.8 2013/06 - 17 - lrc k bick sdto tbsd tmblr 50%dvdd 50%dvdd 50%dvdd figure 8. audio interface timing (tdm 1/0 bits = ?00? & master mode) lrc k bick sdto tbsh tmblr 50%dvdd 50%dvdd 50%dvdd tdmi tsd h tsds vih vil tbss figure 9. audio interface timing (except tdm1/0 bits = ?00? & master mode)
[AK5730] rev 0.8 2013/06 - 18 - tcckl csn cclk tcds cdti tcdh tcss c0 a4 tcckh cdto hi-z r/w c1 vih vil vih vil vih vil tcck figure 10. write/read command input timing (4-wire serial mode) tcsw csn cclk cdti d2 d0 tcsh cdto hi-z d1 d3 vih vil vih vil vih vil figure 11. write data input timing (4-wire serial mode) csn cclk tdcd cdto d7 d6 cdti a1 a0 d5 hi-z 50%dvdd vih vil vih vil vih vil figure 12. read data output timing 1 (4-wire serial mode)
[AK5730] rev 0.8 2013/06 - 19 - csn cclk tccz cdto d2 d1 cdti d0 d3 tcsw tcsh 50%dvdd vih vil vih vil vih vil figure 13. read data output timing 2 (4-wire serial mode) thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 14. i 2 c bus timing tpd vil pdn tpdv sdto 50%dvdd vih figure 15. power-down & reset timing
[AK5730] rev 0.8 2013/06 - 20 - operation overview system clock the msn pin selects either master or slave mode. msn pin = ?h? selects master mode and ?l? selects slave mode. in slave mode, mclk, lrck(fs) and bick are required to operate the AK5730. mclk should be synchronized with lrck but the phase is not critical. table 1 shows the relationship between the sampling rate and the frequencies of mclk and bick. the sampling speed is set by fs0 and fs1 bits ( table 3 ). after exiting reset at power-up in slave mode, the AK5730 is in power-down mode until mclk and lrck and bick are input. in master mode, only mclk is required. master clock input frequency should be set with the cks1-0 bits ( table 2 ), and the sampling speed should be set by the fs1-0 bits. after exiting reset at power-up in slave mode, the AK5730 is in power-down mode until mclk are input. lrck mclk (mhz) bick (mhz) fs 256fs 384fs 512fs 64fs 8khz 2.048 3.072 4.096 0.512 32khz 8.192 12.288 16.384 2.048 44.1khz 11.2896 16.9344 22.5792 2.8224 48khz 12.288 18.432 24.576 3.072 table 1. system clock example cks1 bit cks0 bit clock speed 0 0 256fs 0 1 384fs 1 0 512fs (default) 1 1 (reserved) table 2. master clock control (master mode) fs1 bit fs0 bit sampling rate 0 0 24khz ? 48khz (default) 0 1 12khz ? 24khz 1 0 8khz ? 12khz 1 1 8khz ? 12khz (reserved) table 3. sampling rate (fs)
[AK5730] rev 0.8 2013/06 - 21 - master mode and slave mode master mode and slave mode are selected by setting the m/s pin. (?h?=master mode, ?l?=slave mode) in master mode (m/s pin= ?h?), lrck pin and bick pin are output pins. in slave mode (m/s pin= ?l?), lrck pin and bick pins are input pins pll1/0 bits control the pll modes which generates the internal mclk from bick. master clock should be input the 512fs in master mode and bick 512fs output pll mode. (pll1/0 bits = ?11?) pdn m/s pin pll1 bit pll0 bit lrck pin bick pin l l * * input input l h * * ?l? output ?l? output h l 0 0 input input (pll off) h l 0 1 input 64fs input (pll mode) h l 1 0 input 256fs input (pll mode) h l 1 1 input 512fs input (pll mode) h h * * output output (*: don?t care) table 4. lrck and bick pins digital high pass filter the adc has a digital high pass filter for dc offset cancellati on. the cut-off frequency of the hpf is 1.0hz at fs=48khz and scales with the sampling rate (fs). hpf are controlled by the hpe4-1 bits. hpe1 bit hpf l adc1 hpf off h adc1 hpf on (default) hpe2 bit hpf l adc2 hpf off h adc2 hpf on (default) hpe3 bit hpf l adc3 hpf off h adc3 hpf on (default) hpe4 bit hpf l adc4 hpf off h adc4 hpf on (default) table 5. hpf operation setting
[AK5730] rev 0.8 2013/06 - 22 - audio serial interface format eight types of the date formats are available and selected by setting the dif bit and the tdm1-0 bits. in all modes, the serial data is msb first, 2`s complement format. lrck and bick are output in master mode, input in slave mode. mode dif bit tdm1 bit tdm0 bit bick data format 0 0 0 0 64fs stereo mode (iis) (default) 1 0 0 1 256fs tdm256 mode(iis) 2 0 1 0 512fs tdm512 mode(iis) - 0 1 1 - (reserved) 3 1 0 0 64fs stereo mode (left justified) 4 1 0 1 256fs tdm256 mode (left justified) 5 1 1 0 512fs tdm512 mode (left justified) - 1 1 1 - (reserved) table 6. tdm mode setting lrck bick(64fs) sdto1 ( o ) 0 1 2 3 22 23 24 25 0 0 1 tdmi(i) 31 29 30 23 22 1 23:msb, 0:lsb data 1 data 2 don?t care 2 0 2 3 22 23 24 25 0 31 29 30 23 22 1 2 0 1 sdto2 ( o ) 23 22 1 23:msb, 0:lsb data 3 data 4 2 0 23 22 1 2 0 figure 16. mode 0 timing (stereo mode (iis)) lrck (slave) bick (256fs) sdto1 (o) 23 0 data 1 32 bick 256 bick 23 0 data 2 32 bick 23 23 0 data 3 32 bick 23 0 data 4 32 bick lrck (master) tdmi (i) 23 0 data 5 32 bick 23 0 data 6 32 bick 23 23 0 data 7 32 bick 23 0 data 8 32 bick 23 0 data 5 32 bick 23 0 data 6 32 bick 23 0 data 7 32 bick 23 0 data 8 32 bick sdto2 (o) * * (*: optional) figure 17. mode1 timing (tdm256 mode (iis))
[AK5730] rev 0.8 2013/06 - 23 - bick ( 512fs ) sdto1 ( o ) tdm1 ( i ) 23 0 data 1 32 bick data 5 32 bick data 6 32 bick data 7 32 bick data 8 32 bick data 9 32 bick data 10 32 bick data 11 32 bick data 12 32 bick 23 0 data 2 32 bick data 13 32 bick data 14 32 bick data 15 32 bick data 16 32 bick 32 bick 32 bick 32 bick 32 bick 23 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 data 3 32 bick 23 0 data 4 32 bick 23 lrck ( slave ) 512bick lrck ( master ) data 5 32 bick data 6 32 bick data 7 32 bick data 8 32 bick data 9 32 bick data 10 32 bick data 11 32 bick data 12 32 bick data 13 32 bick data 14 32 bick data 15 32 bick data 16 32 bick 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 sdto2 ( o ) * * (*: optional) figure 18. mode2 timing (tdm512 mode (iis)) lrck bick(64fs) sdto ( o ) 0 1 2 3 22 23 24 25 0 0 1 tdmi ( i ) 31 29 30 23 22 1 don?t care 2 0 2 3 22 23 24 25 0 31 29 30 23 22 1 2 0 1 sdto2 ( o ) 23 22 1 23:msb, 0:lsb data 3 data 4 2 0 23 22 1 2 0 23:msb, 0:lsb data 1 data 2 figure 19. mode3 timing (stereo mode (left justified)) lrck (slave) bick (256fs) sdto1 (o) 23 0 data 1 32 bick 256 bick 23 0 data 2 32 bick 23 23 0 data 3 32 bick 23 0 data 4 32 bick lrck (master) tdmi (i) 23 0 data 5 32 bick 23 0 data 6 32 bick 23 23 0 data 7 32 bick 23 0 data 8 32 bick 23 0 data 5 32 bick 23 0 data 6 32 bick 23 0 data 7 32 bick 23 0 data 8 32 bick sdto2 (o) * * figure 20. mode4 timing (tdm256 mode (left justified))
[AK5730] rev 0.8 2013/06 - 24 - bick ( 512fs ) sdto1 ( o ) tdm1 ( i ) 23 0 data 1 32 bick data 5 32 bick data 6 32 bick data 7 32 bick data 8 32 bick data 9 32 bick data 10 32 bick data 11 32 bick data 12 32 bick 23 0 data 2 32 bick data 13 32 bick data 14 32 bick data 15 32 bick data 16 32 bick 32 bick 32 bick 32 bick 32 bick 23 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 data 3 32 bick 23 0 data 4 32 bick 23 lrck ( slave ) 512bick lrck ( master ) data 5 32 bick data 6 32 bick data 7 32 bick data 8 32 bick data 9 32 bick data 10 32 bick data 11 32 bick data 12 32 bick data 13 32 bick data 14 32 bick data 15 32 bick data 16 32 bick 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 sdto2 ( o ) * * (*: optional) figure 21. mode5 timing (tdm512 mode (left justified))
[AK5730] rev 0.8 2013/06 - 25 - tdm cascade mode (1)tdm256mode two devices can be connected in cascades at the tdm256 mode. in figure 22 , the sdto1 pin of device #1 is connected with the tdmi pin of device #2. it is possible to output 8channel tdm data from the sdto1 pin of device # 2 as shown in figure 17 and figure 20 . 48khz 256fs 8ch tdm 256fs or 512fs gnd lrck a k573 0 #1 bick tdmi sdto1 mclk lrc k a k573 0 #2 bic k tdmi sdto1 mcl k figure 22. cascade tdm connection diagram (tdm256 mode) (2)tdm512mode four or less devices can be connected in cascades at the tdm512 mode. in figure 23 , the sdto1 pin of device #1-3 is connected with the tdmi pin of device #2-4. it is possible to output 16 channel tdm data from the sdto1 pin of device #4 as shown in figure 18 and figure 21 . 48khz 512fs 16ch tdm 256fs or 512fs gnd lrck a k573 0 #1 bick tdmi sdto1 mclk lrc k a k573 0 #2 bic k tdmi sdto1 mcl k lrc k a k573 0 #3 bic k tdmi sdto1 mcl k lrck a k573 0 #4 bick tdmi sdto1 mclk figure 23. cascade tdm connection diagram (tdm512 mode)
[AK5730] rev 0.8 2013/06 - 26 - system reset the AK5730 should be reset once by bringing the pdn pin = ?l? upon power-up. the AK5730 is powered up and the internal timing starts clocking by lrck ? ? after exiting the power down state of reference voltage (such as vcom) by mclk. in slave mode, the AK5730 is in power-down mode until mclk and lrck are input. in master mode, the AK5730 is in power-down mode until mclk is input. followi ng all clock inputs, set rstn bit to ?1? after setting microphone bias voltage (mbs3-0 bits). digital attenuator the AK5730 has a channel-independe nt digital attenuator (256 levels, 0.5db st ep). attenuation level of each channel can be set by each the att7-0 bits ( table 7 ). att7-0 attenuation level 00h +12db 01h +11.5db : : 0db(default) -0.5db -1.0db : feh -115.0db ffh mute (- ) table 7. attenuation level of digital attenuator transition time between set values of att7-0 bits can be selected by ats1-0 bits ( table 8 ). transition between set values is the soft transition in mode1/2/3 eliminating a switching noise in the transition. mode ats1 ats0 att speed 0 0 0 3712/fs 1 0 1 928/fs 2 1 0 1856/fs 3 1 1 7424/fs (default) table 8. transition time between set values of att7-0 bits the transition between set values is a soft transition of 3712 levels in mode 0. it takes 3712/fs (77.3ms@fs=48khz) from 00h(0db) to ffh(mute). if the pdn pin goes to ?l?, the a tts are initialized to 00h. the atts also become 00h when rstn bit = ?0?, and fade to their curre nt value when rstn bit returns to ?1?.
[AK5730] rev 0.8 2013/06 - 27 - analog input mode the AK5730 has 4 analog input modes. analog input mode is controlled by lin*1-0 bits. the input mode is fixed by each set. the ac signal is input from in*p/n, and the dc signal is input from inm*p/ n. except for microphone input mode, the input voltage of in*p/n(=1.65vrms (t yp.), differential) should be adjusted with external resistors. as for the accuracy of external resistance, 0.1% is required for cmrr. the input voltage of inm*p/n(=avdd) s hould be adjusted with external resi stors. fault conditions are calculated digitally, so the value of external resistance is fixed to 7:3. the input voltage of inm*p/n becomes 30% of vdc+/-. as for the accuracy of external resistance, 0. 1% is required for the accuracy of sar. the full scale of sar is normalized to 11v (@avdd=3.3v ) for calculations of fau lt condition detection. (a) microphone input mode (lin*1-0 bits = ?00?) the microphones are connected in a fully balanced manner. a separate cable shield for each microphone may be connected to chassis ground. in this use case, a gain correction of 9.5db by gain* bit = ?1? is available. parameter specification remarks mic impedance 1 - 2kohm, 10kohm(max) mic audio output 10...100mvrms, 1.75vrms(max) interchannel isolation(max) of microphone inputs 70db mic phantom voltage(vbias) 5v - 9v depending on type of microphone mic supply current 0.1 - 10ma per microphone depending on type of microphone resistors (symmetrical) 200 - 10k table 9 specification(microphone input mode) maximum interchannel isolation of microphone inputs is 70db.the isolation depends on mpwr common impedance. in figure 24 , the microphone impedance and the microphone bias resistance is 2k ohm and mpwr voltage is 8.0v. at this time, mpwr common impedance should be 0.2 ohms or less. +8.0v isolation measured 2kohm mpwr max: 0.2ohm 1khz sin wave 100mvpp AK5730 2kohm 2kohm 2kohm 2kohm(mic) 2kohm(mic) figure 24. interchannel isolation of microphone inputs
[AK5730] rev 0.8 2013/06 - 28 - different types of microphones can be connected at the same time, with the same phantom voltage. in*+ in*- mic bias, cp mic figure 25. microphone input mode(in*+/- pins) for fault conditions, refer to table 10 and figure 26 . fault conditions conditions positive/negative input s horted to vbat vdc+/- vbias + vth positive/negative input shorted to gnd vdc+/- vth pos. and neg. inputs shorted |vdc+ - vdc-| vth positive input open vbias - vth vdc+ vbias + vth negative input open vdc+/- vth note. it is not possible to disti nguish ?positive/negative input shorted to gnd? and ?negative input open?. vth: error monitor threshold voltage. vth is set by table 18 . table 10 fault conditions (microphone input mode) inm*p inm*n mic bias, cp mic r1 r2 vdc- vdc+ vbias figure 26. microphone input mode (in*mp/n pins)
[AK5730] rev 0.8 2013/06 - 29 - (b)line and phone input mode (lin*1-0 bits = ?01?) the stereo line input is a quasi-differential input, r and l sh are a common return. line return, phone return and head unit ground may be isolated from each other. c ombinations of two stereo line input s, one stereo line and one stereo phone inputs are possible. any combination of inputs shown left may be connected in the applications. parameter specification remarks stereo line input voltage 1 - 3v rms (depending on customer) phone input voltage 0.1 - 3v rms (depending on customer) table 11 specification (line and phone input mode) in*p in*n mic bias, cp line or phone r1 r2 ac r2 figure 27. line and phone input mode(in*p/n pins) for fault conditions, refer to table 12 and figure 28 . the ?pos. and neg. inputs shorted state (r2/(2r1+r2)) * vbias? is detected based on sar threshold a(tha12-01 bits). the threshold a is a 12bit straight bina ry code which the full scale is 11v. fault conditions conditions positive/negative input s horted to vbat vdc+/- vbias + vth positive/negative input shorted to gnd vdc+/- vth pos. and neg. inputs shorted r2/(2r1+r2) * vbias ?vth vdc+ vdc- r2/(2r1+r2) * vbias + vth positive input open vbias - vth vdc+ vbias + vth negative input open vdc+/- vth note. it is not possible to disti nguish ?positive/negative input shorted to gnd? and ?negative input open?. note. the ?pos. and neg. inputs shorted? is a condition that occurs when there is no input signal, and dc voltage is not supplied by the input signal. table 12 fault conditions (line and phone input mode) inm*p inm*n mic bias, cp line or phone r1 r2 ac vdc- vdc+ vbias figure 28. line and phone input mode (in*mp/n pins)
[AK5730] rev 0.8 2013/06 - 30 - (c) booster input mode (lin*1-0 bits = ?10?) the booster inputs are directly driven by a standard automotive power amp, either by a class ab, a class sb (i) or even by a class d amplifier. the connection is made in a fully balanced manner. in case of using a class sb (i) amplifier, the input voltage may contain common mode signal inside the audio ba ndwidth due to switching from bridge to single ended mode and vice versa. booster inputs may share a quad-adc w ith any other input type (line, phone and microphone). parameter specification remarks input voltage typ. 10.0v rms @ battery voltage <14.4v input voltage max. 11.7v rms @ battery voltage =16.5v table 13 specification (booster input mode) in*p in*n mic bias, cp power amp r1 r3 amp r2 vbat figure 29. booster input mode (in*p/n pins) diagnostic functions are performed by the external amplifier. a simple check can be made, whether the input is connected or not. input is connected to amp output: vdc+ = vdc- = vbat / 2. refer to note 14 and figure 30 about fault conditions. the ?input open state ((r2+r3)/(r1+r2+r3) * vbias) and (r2/(r1+r2+r3) * vbias)? are detected based on sar threshold b and c (thb12-01 bits, thc12-01 bits). the threshold b and c are 12bit straight binary codes, which the full scale is 11v (typ.). fault conditions conditions positive input open (r2+r3)/ (r1+r2+r3) * vbias ?vth vdc+ (r2+r3)/(r1+r2+r3) * vbias +vth negative input open r2/(r1+r2+r3) * vbias ? vth vdc- r2/(r1+r2+r3) * vbias + vth note. positive/negative input open conditions are statuses when there is no input si gnal and dc voltage is not supplied by the input signal. table 14 fault conditions (booster input mode) inm*p inm*n mic bias, cp power amp r1 r3 amp r2 vbat vbias figure 30. booster input mode (inm*p/n pins)
[AK5730] rev 0.8 2013/06 - 31 - (d) internal unbalanced sources mode (lin*1-0 bits = ?11?) max. unbalanced input voltage < 2v rms a digital gain correction of 9.5db can be applied to unbala nced inputs. unbalanced input should be possible on either positive and negative inputs. in this mode, no di agnosis is performed for internal connections. (e) vbatm pin the input voltage of the vbatm pin should be adjusted with external resistors as below. the input voltage range is 0 to avdd. when the input is avdd voltage (=3.3v typ.), the sar outputs full-scale data(typ.) ex.) avdd=3.3v r1=2 m , r2=360k when battery voltage is 21.6v, the voltage at vbatm pin becomes 3.3v and the sar outputs full-scale data. battery = 21.6v full-scale vbatm r1 r2 battery figure 31. vbatm pin
[AK5730] rev 0.8 2013/06 - 32 - error detection the following seven events cause the int pin to show the status of the interrupt condition. when the pdn pin is ?l?, the int pin goes to ?hi-z?. 1. open: open circuit 2. shtd: short between the positive and negative mic input 3. shtg: short to ground 4. shtv: short to vbat 5. ovcr1: mic bias over-current(90ma(typ)) of booster 6. ovcr2: charge pump over-current(600ma(typ)) of booster 7. ovtp: over-temp(165 degrees(typ)) of booster the int pin outputs an ored signal based on the above seven interrupt events. when error information is masked, the interrupt event does not affect the operation of the int pin. this pin should be connected to dvdd (typ. 3.3v) or lower voltage via a 10kohm resistor. once the int pin goes to ?l?, it remains ?l? until writing intr bit = ?1?. after writing ?1? to intr bit, it automatically returns to ?0?. open, shtd, shtg, shtv, ovcr and ovtp bits in address 07-0bh indicate the interrupt status events above in real time. once they go to ?1?, it stays ?1? until writing intr bit = ?1?. when mshtv*, mshtg*, mshtd*, mopen* (*: 1-4) bits (address=0c-0fh) go to "1", error information at shtv*, shtg*, shtd*, open* bits can not be masked but does not affect the operation of the int pin. ( table 16 ) when over-temperature (ovtp) or ove r-current (ovcr1, ovcr2) is detected, the AK5730 disable the block listed on table 15 . unless the error is due to over-temperature or over-curre nt, error detection is restarted by writing intr bit = ?1?. when the error is due to over-temperature or over-c urrent, restart the AK5730 by the pdn pin or rstn bit. int detection cpuif refblk pll vcmiref cp mic adc saribuf sar micdiags sar err a a a a a a a a a a tsd overtemp. a a a a l a a a a mic overcurrent + a a a a l a a a a mic overcurrent - a a a a cp overcurrent a a a a l a a: active block, l: active in low power mode, : power down table 15. block conditions on error detection unmasked event mask ed event int pin not detected not detected detected hi-z detected l (goes ?hi-z? after writing intr bit = ?1?) table 16. error handling in serial control mode
[AK5730] rev 0.8 2013/06 - 33 - rstn read(up) int error event fault no rmal monitor bit write ?1? cycle normal intr err or ha nd li ng (1) (2) (3) (4) figure 32 error detection timing notes: (1) execute error detection from 1ch to 8ch (in 1p~in4p, in1n~in4n pins) in this order. (2) after the error detection from 1ch to 8ch, the error detection results are ored and reflected to int pins. indication of int pins can be masked by mshtv*, mshtg*, mshtd*, mopen* (*: 1-4) bits (address= 0c-0fh). (3) error monitor registers are reset by setting intr bit to ?1? after all error conditions are removed. (4) when the detected error is due to over-temperature or over-current, restart the AK5730 by the pdn pin or rstn bit.
[AK5730] rev 0.8 2013/06 - 34 - int pin = "l" ye s initialize pdn pin ="l" to "h" register setting read ?07h? to ?0bh? no write rstn bit = ?1? ? ovtp? ?ovcr2? ?ovcr 1? bit =?1? ye s no in tr (error handli ng) (error handling) figure 33 error handling sequence example
[AK5730] rev 0.8 2013/06 - 35 - power up/down sequence the each block of the AK5730 is placed in power-down mode by bringing the pdn pin to ?l? and both digital filters are reset at the same time. the pdn pin =?l? also resets the cont rol registers to their default values. in power-down mode, the sdto pin goes to ?l?. this reset must always be executed after power-up. in slave mode, after exiting reset at power-up and etc., th e adc starts operation from the rising edge of lrck after mlck inputs. the AK5730 is in power-down mode until mclk and lrck and bick are input. the analog initialization cycle of adc starts after exiting the power-down mode. therefore, the output data, sdto becomes available after 1041/fs cycles of lrck clock. figure 34 shows the sequences of the power-down and the power-up. when rstn bit = ?0?, all circuits are powered- down but the internal register are not initialized. (2) pll a dc internal state power-down 1041/fs init cycle normal operation (7) (4) 0v micpwr pin normal operation 0v a dc in (analog) a dc out (digital) ?0?data (5) gd gd (8) ?0?data power (3) don?t care clock in mclk,lrck,bick don?t care (1.67 x vdd) x2 2vp pin (9) (6) (9) vp pin 1.67 x vdd vdd micref pin pdn pin (1) normal operation vdd vdd vdd vdd figure 34 power-up/down sequence example
[AK5730] rev 0.8 2013/06 - 36 - notes: (1) the pdn pin should be set to ?h? after all powers (dvdd, avdd) are supplied. the AK5730 requires 150ns or longer ?l? period for a certain reset. supply the power during the pdn pin = ?l?. (2) set rstn bit to ?1? after setting microphone bias voltage (mbs3-0 bits). (3) power-on the pll circuit:(pll mode) pll1-0 bits = ?01? or ?10? or ?11? & bick is input. pll is locked within 1 - 2ms (4) power-on the micref circuit: the cvp1 pin is charged up. the micref pin becomes (1.67 x vdd) x 2 within about 20 - 40ms. (5) adc outputs ?0? data in power-down state. (6) power-on the charge pump circuit1/2: (normal mode) pdn pin = ?l? ?h?(or pll is locked) & mclk, bick, lrck is input.(normal mode) (pll mode) pll is locked. the cvp1 pin becomes 1.67 x vdd within about 4 - 8ms. the cvp2 pin becomes (1.67 x vdd) x 2 within about 4 - 8ms. (7) the analog block of adc is initialized after exiting the power-down state. (8) digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay (gd). (9) charge pump circuit power down: pdn pin = ?h? ? ?l? the cvp1/2 pin becomes vdd according to a flying capacitor and internal resi stor. the internal resistor is 50k ? (typ). therefore, when the cvp1/2 pin has a flying capacitor of 2.2f, the time constant is 110ms (typ).
[AK5730] rev 0.8 2013/06 - 37 - serial control interface (1) 4-wire serial control mode (spi pin = ?h?) the internal registers may be either written or read by the 4-wire p in terface pins: csn, cclk, cdti & cdto. the data on this interface consists of ch ip address (1bit, c1 is fixed to ?1?) , read/write (1bit), register address (msb first, 6bits) and control data (m sb first, 8bits). address and data is clocked in on the rising edge of cclk and data is clocked out on the falling e dge. for write operations, data is latched after the 16th rising edge of cclk, after a high-to-low transition of csn. for read operations, the cdto output goes high impedance after a low-to-high transition of csn. the maximum speed of cclk is 5mhz. the pdn pin= ?l? resets the registers to their default values. cdti cclk csn c1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w a5 a0 d0 d1 d2 d3 cdto hi-z write cdti c1 d4 d5 d6 d7 a1 a2 a3 a4 r/w a5 a0 d0 d1 d2 d3 cdto hi-z read d4 d5 d6 d7 d0 d1 d2 d3 hi-z c1: chip address (fixed to ?1?) r/w: read/write (0:read, 1:write) a5-a0: register address d7-d0: control data figure 35. 4-wire serial control i/f timing (2). i 2 c bus control mode (spi pin = ?l?) the AK5730 supports the fast-mode i 2 c-bus (max: 400khz). (2)-1. write operations figure 36 shows the data transfer sequence of the i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 42 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant five bits of the slave address are fixed as ?00100?. the next bits are cad1 and cad0 (device address bit). this bit identifies the specific device on the bus. the hard-wired input pins (cad1/0 pins) set these device address bits ( figure 37 ). if the slave address matches that of the AK5730, the AK5730 generates an acknowledge and the operation is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 43 ). r/w bit = ?1? indicates that the read operation is to be executed. ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the AK5730. the format is msb first, and those most significant 2-bits are fixed to zeros ( figure 38 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 39 ). the AK5730 generates an acknowledge after each by te is received. data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 42 ). the AK5730 can perform more than one by te write operation per sequence. after receipt of the third byte the AK5730 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the
[AK5730] rev 0.8 2013/06 - 38 - write cycle after the first data byte is transferred. after r eceiving each data packet the inte rnal 6-bit address counter is incremented by one, and the next data is automatically taken into the next addr ess. if the address exceeds 2dh prior to generating a stop condition, the address counter will ?roll over? to 00h and th e previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only be changed when the clock signal on the scl line is low ( figure 44 ) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 36. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 cad1 cad0 r/w (those cad1/0 should match with cad1/0 pins) figure 37. the first byte 0 0 a5 a4 a3 a2 a1 a0 figure 38. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 39. byte structure after the second byte
[AK5730] rev 0.8 2013/06 - 39 - (2)-2. read operations set the r/w bit = ?1? for the read operation of the AK5730. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cy cle after the receipt of the first data word. after receiving each data packet the inte rnal 6-bit address counter is increm ented by one, and the next data is automatically taken into the next address. if the address exceeds 2dh prior to generating a stop condition, the address counter will ?roll over? to 00h and the data of 00h will be read out. the AK5730 supports two basic read operations: current address read and random address read. (2)-2-1. current address read the AK5730 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address ?n?, the next current read operation would access data from the address ?n+1?. after receipt of the slave address with r/w bit ?1?, the AK5730 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknow ledge but generates a stop condition instead, the AK5730 ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) n a c k p s t o p data(n) m a s t e r m a s t e r m a s t e r m a s t e r m a s t e r figure 40. current address read (2)-2-2. random address read the random read operation allows the master to access any me mory location at random. prior to issuing a slave address with the r/w bit =?1?, the master must execute a ?dummy? write operation first. th e master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit =?1?. the AK5730 then generates an acknowledge, 1 byte of data and increments the internal a ddress counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the AK5730 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k n a c k m a s t e r m a s t e r m a s t e r m a s t e r figure 41. random address read
[AK5730] rev 0.8 2013/06 - 40 - scl sda stop condition start condition s p figure 42. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 43. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 44. bit transfer on the i 2 c-bus
[AK5730] rev 0.8 2013/06 - 41 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h general setting 1 cks1 cks0 at s1 ats0 dif tdm1 tdm0 rstn 01h general setting 2 mbs3 mbs2 mbs1 mbs0 fs1 fs0 pll1 pll0 02h input mode lin41 lin40 lin31 lin30 lin21 lin20 lin11 lin10 03h adc1 volume control att17 att16 att15 att14 att13 att12 att11 att10 04h adc2 volume control att27 att26 att25 att24 att23 att22 att21 att20 05h adc3 volume control att37 att36 att35 att34 att33 att32 att31 att30 06h adc4 volume control att47 att46 att45 att44 att43 att42 att41 att40 07h monitor summary 0 0 0 0 adc4 adc3 adc2 adc1 08h monitor adc1 0 ovtp ovcr2 ovcr1 shtv1 shtg1 shtd1 open1 09h monitor adc2 0 0 0 0 shtv2 shtg2 shtd2 open2 0ah monitor adc3 0 0 0 0 shtv3 shtg3 shtd3 open3 0bh monitor adc4 0 0 0 0 shtv4 shtg4 shtd4 open4 0ch mask adc1 0 0 0 0 mshtv1 mshtg1 mshtd1 mopen1 0dh mask adc2 0 0 0 0 mshtv2 mshtg2 mshtd2 mopen2 0eh mask adc3 0 0 0 0 mshtv3 mshtg3 mshtd3 mopen3 0fh mask adc4 0 0 0 0 mshtv4 mshtg4 mshtd4 mopen4 10h threshold setting open 0 0 0 0 top4 top3 top2 top1 11h threshold setting shtd 0 0 0 0 tsd4 tsd3 tsd2 tsd1 12h threshold setting shtg 0 0 0 0 tsg4 tsg3 tsg2 tsg1 13h threshold setting shtv 0 0 0 0 tsv4 tsv3 tsv2 tsv1 14h int setting std4 std3 std2 std1 0 0 0 intr 15h adc hpf gain4 gain3 gain2 gain1 hpf4 hpf3 hpf2 hpf1 16h sar thresh a high byte tha12 tha11 tha10 tha09 tha08 tha07 tha06 tha05 17h sar thresh a low byte tha04 tha03 tha02 tha01 0 0 0 0 18h sar thresh b high byte thb12 thb11 thb10 thb09 thb08 thb07 thb06 thb05 19h sar thresh b low byte thb04 thb03 thb02 thb01 0 0 0 0 1ah sar thresh c high byte thc12 thc11 thc10 thc09 thc08 thc07 thc06 thc05 1bh sar thresh c low byte thc04 thc03 thc02 thc01 0 0 0 0 1ch sar in1+ high byte 1p12 1p11 1p10 1p09 1p08 1p07 1p06 1p05 1dh sar in1+ low byte 1p04 1p03 1p02 1p01 0 0 0 0 1eh sar in1- high byte 1n12 1n11 1n10 1p09 1n08 1n07 1n06 1n05 1fh sar in1- low byte 1n04 1n03 1n02 1n01 0 0 0 0 20h sar in2+ high byte 2p12 2p11 2p10 2p09 2p08 2p07 2p06 2p05 21h sar in2+ low byte 2p04 2p03 2p02 2p01 0 0 0 0 22h sar in2- high byte 2n12 2n11 2n10 2n09 2n08 2n07 2n06 2n05 23h sar in2- low byte 2n04 2n03 2n02 2n01 0 0 0 0 24h sar in3+ high byte 3p12 3p11 3p10 3p09 3p08 3p07 3p06 3p05 25h sar in3+ low byte 3p04 3p03 3p02 3p01 0 0 0 0 26h sar in3- high byte 3n12 1n11 3n10 3p09 3n08 3n07 3n06 3n05 27h sar in3- low byte 3n04 3n03 3n02 3n01 0 0 0 0 28h sar in4+ high byte 4p12 4p11 4p10 4p09 4p08 4p07 4p06 4p05 29h sar in4+ low byte 4p04 4p03 4p02 4p01 0 0 0 0 2ah sar in4- high byte 4n12 4n11 2n10 4n09 4n08 4n07 4n06 4n05 2bh sar in4- low byte 4n04 4n03 4n02 4n01 0 0 0 0 2ch sar vbat high byte vb12 vb11 vb10 vb09 vb08 vb07 vb06 vb05 2dh sar vbat low byte vb04 vb03 vb02 vb01 0 0 0 0 note: for addresses from 2eh to 3fh, data is not written. when the pdn pin goes to ?l?, all registers are initialized to their default values. when rstn bit is set to ?0?, the internal timing is reset, but registers are not initialized to their default values.
[AK5730] rev 0.8 2013/06 - 42 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h general setting cks1 cks0 ats1 ats0 dif tdm1 tdm0 rstn r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 0 0 0 0 rstn: internal timing reset 0: reset. registers are not initialized. (default) 1: normal operation tdm1-0: tdm mode select ( table 6 ) 00: normal mode. (default) 01: tdm256 mode 10: tdm512 mode 11: reserved dif: data format setting ( table 6 ) 0: iis. (default) 1: left justified ats1-0: digital attenuator transition time setting ( table 8 ) default: ?00?, mode 0 cks1-0: master clock setting in master mode. refer to table 2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h general setting 2 mbs3 mbs2 mbs1 mbs0 fs1 fs0 pll1 pll0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pll1-0: pll mode setting ( note 4 ) 00: normal mode. pll off. (default) 01: pll mode (bick=64fs) 10: pll mode (bick=256fs) 11: pll mode (bick=512fs) fs1-0: sampling frequency setting ( table 3 ) 00: 24k-48khz (default) 01: 12k-24khz 10: 8k-12khz 11: (reserved)
[AK5730] rev 0.8 2013/06 - 43 - mbs3-0: mic bias voltage setting mbs3-0 bias voltage 00h 5v (default) 01h 5.5v 02h 6v 03h 6.5v 04h 7v 05h 7.5v 06h 8v 07h 8.5v 08h 9v 09h hi-z 0ah-0fh (reserved) table 17. mic bias voltage setting addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h input mode lin41 lin40 lin31 lin30 lin21 lin20 lin11 lin10 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 lin*1-*0: mic/line select for each adc* 00: mic mode (default) 01: line and phone mode 10: booster input mode 11: internal unbalanced sources mode. no diagnosis is performed for internal connections. addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h adc1 volume control att17 a tt16 att15 att14 att13 att12 att11 att10 04h adc2 volume control att27 a tt26 att25 att24 att23 att22 att21 att20 05h adc3 volume control att37 a tt36 att35 att34 att33 att32 att31 att30 06h adc4 volume control att47 a tt46 att45 att44 att43 att42 att41 att40 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 1 0 0 0 att*7-*0: adc* volume control refer to table 7 addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h monitor summary 0 0 0 0 adc4 adc3 adc2 adc1 r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 adc4-1: error monitor for each adc 0: no error detected. 1: error detected. set int pin ?h i-z?. returns to ?l? wh en intr bit = ?1?.
[AK5730] rev 0.8 2013/06 - 44 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h monitor adc1 0 0 ovtp1 ovcr1 shtv1 shtg1 shtd1 open1 09h monitor adc2 0 0 0 0 shtv2 shtg2 shtd2 open2 0ah monitor adc3 0 0 0 0 shtv3 shtg3 shtd3 open3 0bh monitor adc4 0 0 0 0 shtv4 shtg4 shtd4 open4 r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 error monitor. 0: no error detected. 1: error detected. set adcx bit ?1? if unmasked. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch mask adc1 0 0 0 0 mshtv1 mshtg1 mshtd1 mopen1 0dh mask adc2 0 0 0 0 mshtv2 mshtg2 mshtd2 mopen2 0eh mask adc3 0 0 0 0 mshtv3 mshtg3 mshtd3 mopen3 0fh mask adc4 0 0 0 0 mshtv4 mshtg4 mshtd4 mopen4 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 error monitor mask. 0: no mask. 1: mask error. addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h threshold setting open 0 0 0 0 top3 top2 top1 top0 11h threshold setting shtd 0 0 0 0 tsd3 tsd2 tsd1 tsd0 12h threshold setting shtg 0 0 0 0 tsg3 tsg2 tsg1 tsg0 13h threshold setting shtv 0 0 0 0 tsv3 tsv2 tsv1 tsv0 r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 error monitor threshold setting threshold voltage is proportional to avdd voltage. this value is set in digital code. the threshold voltage is a 12bit stra ight binary code which the full scale is avdd/3 (11v@avdd=3.3v). the monitored voltage is multiplied by 0.3 by an external resist or and input to the voltage m onitoring pin. therefore, the threshold voltage range is from +100mv/3(=+30mv) to +900mv/3(=+300mv) at the input pin. bit3-0 threshold voltage 00h +100mv 01h +200mv 02h +300mv (default) 03h +400mv 04h +500mv 05h +600mv 06h +700mv 07h +800mv 08h +900mv 09h-0fh (reserved) table 18. error monitor threshold setting.
[AK5730] rev 0.8 2013/06 - 45 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 14h int setting std4 std3 std2 std1 0 0 1 intr r/w r/w r/w r/w r/w rd rd rd r/w default 0 0 0 0 0 0 1 0 intr: int pin reset 0: normal operation (default) 1: reset. error monitor registers(07-0bh) are initialized. std1-4: adc1-4 mode setting 0: differential mode(default) 1: single-ended mode . when std* bit =?1?, single-ended in*p pin, in*n pin must be connected to signal common. addr register name d7 d6 d5 d4 d3 d2 d1 d0 15h adc hpf gain4 gain3 gain2 gain1 hpf4 hpf3 hpf2 hpf1 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 1 1 1 1 hpf4-1: adc1-4 hpf on/off ( table 5 ) 0:adc* hpf off 1:adc* hpf on (default) gain4-1: adc1-4 differe ntial input voltage setting 0: 1.68vrms (default) 1: 0.56vrms. when gain*bit = ?1?, input voltage is amplified threefold (+9.5db) in order to adjust full scale range to that of the default condition, attenuation level of each channel should be set at -9.5db by the att7-0 bits ( table 7 ).
[AK5730] rev 0.8 2013/06 - 46 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 16h sar thresh a high byte tha12 tha11 tha10 tha09 tha08 tha07 tha06 tha05 17h sar thresh a low byte tha04 tha03 tha02 tha01 0 0 0 0 18h sar thresh b high byte thb12 thb11 thb10 thb09 thb08 thb07 thb06 thb05 19h sar thresh b low byte thb04 thb03 thb02 thb01 0 0 0 0 1ah sar thresh c high byte thc12 thc11 thc10 thc09 thc08 thc07 thc06 thc05 1bh sar thresh c low byte thc04 thc03 thc02 thc01 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 sar raw data threshold a/b/c. a: r2/(2r1+r2)*vbias:pos. and neg. inputs shorted in line and phone mode. b: (r2+r3)/(r1+r2+r3)*vbias: input open in booster input mode. c: r2/(r1+r2+r3)*vbias: input open in booster input mode. addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ch sar in1+ high byte 1p12 1p11 1p10 1p09 1p08 1p07 1p06 1p05 1dh sar in1+ low byte 1p04 1p03 1p02 1p01 0 0 0 0 1eh sar in1- high byte 1n12 1n11 1n10 1p09 1n08 1n07 1n06 1n05 1fh sar in1- low byte 1n04 1n03 1n02 1n01 0 0 0 0 20h sar in2+ high byte 2p12 2p11 2p10 2p09 2p08 2p07 2p06 2p05 21h sar in2+ low byte 2p04 2p03 2p02 2p01 0 0 0 0 22h sar in2- high byte 2n12 2n11 2n10 2n09 2n08 2n07 2n06 2n05 23h sar in2- low byte 2n04 2n03 2n02 2n01 0 0 0 0 24h sar in3+ high byte 3p12 3p11 3p10 3p09 3p08 3p07 3p06 3p05 25h sar in3+ low byte 3p04 3p03 3p02 3p01 0 0 0 0 26h sar in3- high byte 3n12 1n11 3n10 3p09 3n08 3n07 3n06 3n05 27h sar in3- low byte 3n04 3n03 3n02 3n01 0 0 0 0 28h sar in4+ high byte 4p12 4p11 4p10 4p09 4p08 4p07 4p06 4p05 29h sar in4+ low byte 4p04 4p03 4p02 4p01 0 0 0 0 2ah sar in4- high byte 4n12 4n11 2n10 4n09 4n08 4n07 4n06 4n05 2bh sar in4- low byte 4n04 4n03 4n02 4n01 0 0 0 0 2ch sar vbat high byte vb12 vb11 vb10 vb09 vb08 vb07 vb06 vb05 2dh sar vbat low byte vb04 vb03 vb02 vb01 0 0 0 0 r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 sar raw data readout. when reading these registers, always read the high byte first. the low byte is only updated when the high byte is read. this ensures that the values read from the two registers co me from the same 12-bit word.
[AK5730] rev 0.8 2013/06 - 47 - system design figure 45 shows the system connection diagram example. micro sdto1 lrlk bick iis tdm out iic or spi i/f sda/cdti scl/cclk hpf, lpf, gain in1p in1n mic bias, cp adc4 sar adc in4p in4n mic. diags cad0/csn mux 1 2 7 8 mic line tdmi pll int cad1/cdto vbatm 9 batter y sdto2 vref pdn adc1 mclk mux mclk cp2 cn2 cvp1 msn cp1 cn1 cvp2 inm1p inm1n inm4p inm4n controller 0.1u vss2 dvdd 10u + 0.1u vss1 avdd 10u + 2.2u 2.2u 1u 1u 1u 1u 1u + + 2.2u 2.2u 10k dvdd + - + - spi amp amp figure 45. typical connection diagram grounding and power supply decoupling avdd should be supplied from an analog supply unit with low im pedance and be separated from system digital supply. an electrolytic capacitor of 10 f parallel with a 0.1 f ceramic capacitor should be attached to avdd, dvdd, vss1 and vss2 pin to eliminate the effects of high frequency noise. the 0.1 f ceramic capacitor should be placed as near to dvdd as possible.
[AK5730] rev 0.8 2013/06 - 48 - package(tbd) 1 12 48 13 7.0 9.0 7.0 9.0 0.22 0.08 48pin lqfp(unit: mm) 0.10 37 24 25 36 0.09 0.20 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 0.30 ~ 0.75 0.5 s s m package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatmen t: solder (pb free) plate
[AK5730] rev 0.8 2013/06 - 49 - marking a k5730vq xxxxxxx 1 1) pin #1 indication 2) marking code: AK5730vq 3) date code: xxxxxxx (7 digits)
[AK5730] rev 0.8 2013/06 - 50 - important notice 0. asahi kasei microdevices corporation (?akm?) reserves the right to make changes to the information contained in this document without noti ce. when you consider any use or application of akm product stipulated in this document (?product?), please make inquiries the sales office of akm or authorized distributors as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm products. akm neither makes warranties or representations with respect to the accuracy or complete ness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use of such information contained in this document in your product design or applications. akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliab ility and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear fac ilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control co mbustions or explosions, safety devices, elevators and escalators, devices related to electric power, and e quipment used in finance-related fields. do not use product for the above use unless specifically agreed by akm in writing. 3. though akm works continually to improve the pr oduct?s quality and reliability, you are responsible for complying with safety standards and for provi ding adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction wea pons). when exporting the products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. the products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohib ited under any applicable domestic or foreign laws or regulations. 5. please contact akm sales representative for details as to environmental matters such as the rohs compatibility of the product. please use the product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assumes no liability for damages or losses occurring as a result of noncompliance with applicab le laws and regulations. 6. resale of the product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warra nty granted by akm for the product and shall not create or extend in any manner whatsoever, any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm.

▲Up To Search▲

Price & Availability of AK5730

	To Download AK5730 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .